The present disclosure relates to a presumably defective portion decision apparatus, a presumably defective portion decision method, a fabrication method for a semiconductor device and a program in which, after a polishing step executed after a deposition step in a fabrication process for a semiconductor device, a result of the polishing is evaluated based on measurement, prediction or the like to carry out decision of a presumably defective portion.
In related art, as a technique adapted to achieve higher integration of a semiconductor integrated circuit, a smoothing process is carried out upon production of a semiconductor integrated circuit. As a smoothing processing technique, a chemical mechanical polishing method (hereinafter referred to as “CMP method”) is available.
A concept of a polishing apparatus configured to carry out the CMP method is described below. FIG. 1 is a schematic view showing an example of a configuration of a polishing apparatus.
Referring to FIG. 1, a polishing apparatus 1 shown includes, as principal components thereof, a polishing plate 2, a substrate holding table 4 and an abrasive slurry supplying system 5.
The polishing plate 2 is supported on a polishing plate rotating shaft 2A and has a polishing pad 3 on a surface thereof.
The substrate holding table 4 is disposed above the polishing plate 2 and supported on a substrate holding table rotating shaft 4A. For example, where a substrate 7 on which a semiconductor integrated circuit is formed is polished, the substrate 7 is placed on the substrate holding table 4. The substrate holding table rotating shaft 4A is attached to a polishing pressure adjustment mechanism not shown configured to urge the substrate holding table 4 in a direction toward the polishing pad 3.
The polishing plate 2 is rotated while abrasive slurry 6 contained in an abrasive slurry container 5A of the abrasive slurry supplying system 5 and containing abrasive therein is supplied to the polishing pad 3 through an abrasive slurry introduction path 5B. At the same time, the polishing pressure of the substrate 7 against the polishing pad 3 is adjusted by the polishing pressure adjustment mechanism while the substrate 7 placed on the substrate holding table 4 is rotated. Consequently, a surface of the substrate 7 can be polished.
It is very significant, in order to solve a problem in fabrication of a semiconductor device at an early stage and reduce the fabrication cost, to predict, when a thin film is flattened after it is formed on a circuit pattern formed on the substrate 7, what thickness the thin film comes to have after flattened. Further, information of a sectional structure of a semiconductor device is used from a point of view of analysis of a characteristic of a semiconductor device, namely, timing convergence of a semiconductor integrated circuit, particularly from a point of view of resistance capacitance (RC) extraction. Therefore, by predicting a value of the thickness of a thin film formed on a circuit pattern to be flattened, it is possible to reduce time for timing convergence and feed back the value to a layout such as dummy fill.
As a method adapted to predict film formation and a polishing process, many simulation techniques have been proposed. For example, a method of detecting various kinds of defects caused by a circuit pattern in advance, a simulation technique in a case where the polishing pressure varies with respect to time passage and so forth have been proposed. Further, a method of carrying out level difference prediction after polishing to extract a critical portion of a film has been proposed.
Recently, a simulation technique taking not only polishing of a noticed film but also an underlying layer or layers into consideration for super refinement of a device, increase in strictness of a smoothing specification and so forth has been proposed (for example, refer to Japanese Patent Laid-Open No. 2008-10741).
Further, from a point of view of a layout, a technique automatically inserting, after a critical portion of a film is extracted by a simulation, a dummy in a unit of a mesh within a range within which it does not have influence on an electric characteristic of the circuit has been proposed (for example, refer to Japanese Patent No. 2010-140278).